The present invention relates to a trench-type insulated gate bipolar transistor (hereinafter referred to as a xe2x80x9ctrench-type IGBTxe2x80x9d) having a MOS gate, formed of a metal film, an oxide film and a semiconductor, buried in a trench in the surface portion of a semiconductor substrate.
Insulated gate bipolar transistors (IGBT""s) exhibit both the high breakdown voltage and high current characteristics of bipolar transistors and the high frequency characteristics of MOSFET""s. Recently, the breakdown voltage and the capacity of the IGBT""s have been increased, and some high power devices exhibiting a breakdown voltage of from 2500 to 4500 V and a current capacity of from several hundreds to 1800 A have been developed. These high power devices includes a module-type package or a flat package, in which multiple IGBT chips are mounted in parallel.
FIG. 19 is a cross sectional view of a conventional planar IGBT (hereinafter referred to as a xe2x80x9cP-IGBTxe2x80x9d). Referring now to FIG. 19, p-type well regions 2 are formed selectively from one of the major surfaces of a lightly doped (highly resistive) n-type drift layer 1. In the surface portion of p-type well region 2, n-type emitter regions 3 are formed selectively. A gate electrode 10 is formed above the extended portion of p-type well region 2 extended between n-type drift layer 1 and n-type emitter regions 3 with a gate oxide film 6 interposed therebetween. An emitter electrode 11 is in common contact with p-type well regions 2 and n-type emitter regions 3. A p-type collector layer 4 is formed on the other surface of n-type drift layer 1 with a heavily doped n-type buffer layer 5 interposed therebetween. The n-type buffer layer 5 is doped more heavily than n-type drift layer 1. A collector electrode 12 is in contact with p-type collector layer 4.
Now the operation of the P-IGBT is explained. In the turn-on mode, an inversion layer (hereinafter referred to as a xe2x80x9cchannelxe2x80x9d) is created in the surface portion of p-type well region 2 by applying a positive voltage higher than a certain threshold while collector electrode 12 is biased to be positive and emitter electrode 11 is biased to be negative (or grounded). Electrons are injected from n-type emitter region 3 to n-type drift layer 1 through the channel. The injected electrons lower the potential of n-type buffer layer 5 with respect to the potential of p-type collector layer 4. When the forward voltage across the pn junction between n-type buffer layer 5 and p-type collector layer 4 exceeds the barrier layer voltage of about 0.6 V, holes are injected from p-type collector layer 4 to n-type drift layer 1 via n-type buffer layer 5. The injected electrons and holes are accumulated in n-type drift layer 1 so that electrical neutrality may be realized. The accumulated electrons and holes modulate the conductivity of n-type drift layer 1, resulting in a very low resistance of n-type drift layer 1. The resulting very low resistance of n-type drift layer 1 switches the IGBT on. Hereinafter, the electrons and holes accumulated excessively in n-type drift layer 1 in the ON-state of the IGBT will be referred to as the xe2x80x9caccumulated carriersxe2x80x9d. The holes injected from p-type collector layer 4 in the ON-state pass p-type well region 2 and flow out from emitter electrode 11 in contact with p-type well region 2.
The above described operation is the same with that of a pnp-transistor formed of a p-type collector layer 4, an n-type drift layer 1 and a p-type well region 2. The voltage drop between the collector and the emitter caused by a predetermined current (usually, the rated current) in the ON-state of the IGBT is called a xe2x80x9csaturation voltagexe2x80x9d.
In the turn-off mode, the channel between n-type emitter region 3 and n-type drift layer 1 vanishes as the positive voltage applied to gate electrode 10 is reduced. As the channel between n-type emitter region 3 and n-type drift layer 1 vanishes, the electron injection from n-type emitter region 3 stops, and the holes injected from p-type collector layer 4 to n-type drift layer 1 via n-type buffer layer 5 decrease. The accumulated carries in n-type drift layer 1 form pairs in n-type drift layer 1 and vanish. Or, the electrons flow out to collector electrode 12 via p-type collector layer 4, and the holes flow out to emitter electrode 11 via p-type well region 2. As all the accumulated carriers vanish, the resistance of n-type drift layer 1 becomes extremely high, resulting in an OFF-state of the IGBT. The loss caused during the period of transition from the ON-state to the OFF-state is called the xe2x80x9cturn-off lossxe2x80x9d.
As described above, the ON-state and the OFF-state of the IGBT are determined by the behaviors of the electrons and the holes in n-type drift layer 1. When many carriers are accumulated in n-type drift layer 1 in the ON-state, the saturation voltage is low due to low resistance of n-type drift layer 1. However, since the accumulated carriers are too many to remove in turning-off, the turn-off loss is large. When few carriers are accumulated in n-type drift layer 1 in the ON-state, the turn-off loss is small, since the accumulated carriers to be removed are few. However, the saturation voltage is high due to high resistance of n-type drift layer 1.
Thus, there exists a tradeoff relation between the saturation voltage in the conductive state of the IGBT and the turn-off loss caused in turning-off of the IGBT, wherein the saturation voltage or the turn-off loss increases when the turn-off loss or the saturation voltage reduces. For applying IGBT""s to semiconductor conversion apparatuses, it is important to reduce the tradeoff relation between the saturation voltage and the turn-off loss from the view point of reducing the heat loss.
Since the IGBT was invented in early eighties, various measures have been examined to reduce the tradeoff relation between the saturation voltage and the turn-off loss. Typical measures include a buffer layer disposed between a base layer and a collector layer, and a method of controlling the carrier life time in the base layer.
However, it is difficult to reduce the tradeoff relation between the saturation voltage and the turn-off loss only by changing the total amount of the electrons and the holes injected in n-type drift layer 1. The tradeoff relation may be reduced by changing the distributions of the electrons and the holes injected in semiconductor substrate 1. It has been pointed out for reducing the tradeoff relation that it is effective to increase the amount of the carrier accumulated on the side of the emitter electrode of the IGBT.
Recently, an IGBT (hereinafter referred to as a xe2x80x9cT-IGBTxe2x80x9d), that facilitates reducing the tradeoff relation by forming a MOS gate in a trench dug in the surface portion of a semiconductor substrate, has been proposed.
FIG. 20 is a cross sectional view of a conventional T-IGBT. Referring now to FIG. 20, p-type well regions 2 and n-type emitter regions 3 are formed from one of the major surfaces of a lightly doped n-type drift layer 1. A trench 7 extends from the surface of n-type emitter region 3 to n-type drift layer 1. A gate electrode 10 is buried in trench 7 with a gate oxide film 6 interposed therebetween. An n-type buffer layer 5 is on the other major surfaces of n-type drift layer 1, and a p-type collector layer 4 is on n-type buffer layer 5. An emitter electrode 11 is in common contact with n-type emitter regions 3 and p-type well regions 2. A collector electrode 12 is in contact with p-type collector layer 4.
The parameters of an exemplary T-IGBT, the rated voltage thereof is 4500 V and the rated current density thereof is 40 Acmxe2x88x922, are as follows. The specific resistance of n-type drift layer 1 is about 320 xcexa9cm. The thickness of n-type drift layer 1 is 490 xcexcm. The depth of trench 7 is 6 xcexcm. The short side length in the bottom portion of trench 7 is 2 xcexcm. The spacing between adjacent trenches 7 is 10 xcexcm. The surface impurity concentration of p-type well region 2 is 4xc3x971017 cmxe2x88x923. The depth of p-type well region 2 is 5 xcexcm. The surface impurity concentration of n-type emitter region 3 is 1xc3x971020 cmxe2x88x923. The depth of the n-type emitter region 3 is about 0.5 xcexcm. The width of n-type emitter region 3 is 1 xcexcm. The thickness of gate insulation film 6 is 80 nm. The thickness of insulation film 8 is about 1 xcexcm. A life time killer is doped in a part of n-type drift layer 1. The saturation voltage of the T-IGBT is about 6.3 V at the current density of 40 Acmxe2x88x922 and at the temperature of 125xc2x0 C.
The principles of turning-on and turning-off of the T-IGBT is the same with those of the P-IBGT.
However, since the channels are created in the P-IGBT on the emitter electrode side rather than on the side of the pn-junctions between n-type drift layer 1 and p-type well regions 2, depletion layers expanding from the pn-junctions narrow the current path (sometimes referred to as the xe2x80x9cJ-FET effectxe2x80x9d), raising the saturation voltage. Due to the J-FET effect, the tradeoff relation between the saturation voltage and the turn-off loss is more hazardous for the P-IGBT. In contrast, since the channels are created in the T-IGBT on the collector electrode side rather than on the side of the pn-junctions between n-type drift layer 1 and p-type well regions 2, any J-FET effect is not caused.
Therefore, the T-IGBT is advantageous to reduce the tradeoff relation between the saturation voltage and the turn-off loss, since the T-IGBT facilitates reducing the saturation voltage without increasing the turn-off loss.
Since it is necessary to increase the specific resistance and the thickness of n-type drift layer 1 so that the high breakdown voltage of the IGBT may be sustained, the tradeoff relation between the saturation voltage and the turn-off loss becomes worse in the P-IGBT as the breakdown voltage thereof increases than in the T-IGBT.
The p-type well regions 2 in contact with emitter electrode 11 occupy a wider area on the side of emitter electrode 11 in the T-IGBT than in the P-IGBT. Due to this, the holes injected from p-type collector layer 4 tend to diffuse and flow to emitter electrode 11, lowering the accumulated carrier concentration on the side of emitter electrode 11. Therefore, there exists a certain leeway for further reducing the tradeoff relation between the saturation voltage and the turn-off loss.
An injection-enhancement-type insulated gate bipolar transistor (IEGT) and a T-IGBT, including p-type well regions not in electrical contact with an emitter electrode, have been reported as the examples which reduce the tradeoff relation between the saturation voltage and the turn-off loss by increasing the accumulated carrier concentration on the side of emitter electrode 11. However, the reported IEGT and T-IGBT having complicated structures are not suited for mass-production.
In view of the foregoing, it is an object of the invention to provide a trench-type IGBT (T-IGBT) that facilitates reducing the tradeoff relation between the saturation voltage and the turn-off loss by increasing the accumulated carrier concentration on the side of the emitter electrode by a simple structure.
According to an aspect of the present invention, there is provided a trench-type insulated gate bipolar transistor including: a drift layer of a first conductivity type; well regions of a second conductivity type in the surface portion of the drift layer; emitter regions of the first conductivity type in the respective well regions; trenches extending from the emitter regions to the drift layer; gate electrodes, each thereof being buried in each of the trenches with a gate insulation film interposed therebetween; an emitter electrode in common contact with the emitter regions and the well regions; a collector layer of the second conductivity type on the back surface of the drift layer; a collector electrode on the collector layer; the well regions being formed selectively; and the drift layer including extended portions extended between the well regions.
By leaving the portions, wherein the well regions are not formed, in the major surface of the drift layer, the holes injected from the collector layer are prevented from diffusing and flowing out from the emitter electrode, increasing the accumulated carrier concentration on the side of the emitter electrode. The conductivity modulation is enhanced more with increasing accumulated carrier concentration and, as a result, the saturation voltage is reduced.
Advantageously, doped regions of the first conductivity type, doped more heavily than the drift layer, are formed in the portions, wherein the well regions are not formed, of the major surface of the drift layer.
By disposing the doped regions, the holes injected from the collector layer are prevented from diffusing and flowing out from emitter electrode. The injected holes neutralize the electrons in the doped regions. And, the hole concentration in the vicinity of the doped regions is increased, further increasing the accumulated carrier concentration. Due to the combined effects, the accumulated carrier concentration is increased in a wide area on the side of the emitter electrode.
Advantageously, the surface impurity concentration of the doped regions is 1xc3x971016 cmxe2x88x923 or less.
The surface impurity concentration of 1xc3x971016 cmxe2x88x923 or less is not enough to reverse the conductivity type of the well regions. However, the surface impurity concentration of 1xc3x971016 cmxe2x88x923 or less is enough to induce a sufficient amount of holes to increase the hole concentration in the vicinity of the doped regions.
Advantageously, auxiliary gate electrodes are disposed above the respective extended portions of the drift layer extended between the well regions or above the respective doped regions with respective auxiliary gate insulation films interposed therebetween.
By biasing the auxiliary gate electrodes at a positive potential in the ON-state and at zero or a negative potential in the OFF-state, electrons are accumulated in the surface portions of the drift layer beneath the auxiliary gate electrodes. The holes injected from the collector layer are attracted to the portions, wherein the electrons are accumulated, by the Coulomb force, resulting in a high hole concentration. Thus, the accumulated carrier concentration is further increased.
By connecting the gate electrodes with the respective auxiliary gate electrodes, the auxiliary gate electrodes may be biased at a positive potential in the ON-state, and one power supply may be used to apply a bias voltage.
When the trenches have respective portions not surrounded by any well region nor by any emitter region, electrons are accumulated in the surface portions of the side walls of the trenches by applying a voltage to the gate electrodes in the respective trenches. The accumulated electrons increase the hole concentration, further increasing the accumulated carrier concentration.
Advantageously, the trenches are shaped with respective stripes, and the well regions are shaped with respective stripes extending in perpendicular to the stripes of the trenches.
By arranging the stripe-shaped trenches and the stripe-shaped well regions as described above, it is easy to provide the trenches with the portions not surrounded by any well region nor by any emitter region.
Advantageously, the stripe of the well region is divided into rectangles spaced apart form each other by the stripes of the trenches.
Advantageously, the emitter regions are shaped with respective rectangles extending in parallel to the stripes of the trenches.
Advantageously, the emitter regions are shaped with respective rectangles extending in perpendicular to the stripes of the trenches.
Advantageously, the stripe of the trench is divided into rectangles terminated by the well regions, and the emitter regions are arranged along the short sides of the rectangular trenches.
Any of the above described arrangements facilitates providing the trenches with the portions not surrounded by any well region nor by any emitter region.
Advantageously, the ratio Wt/Wp of the bottom width Wt of the trench and the width Wp of the well region between the trenches is set at a value between 1 and 20.
By setting the ratio Wt/Wp as described above, electrons are attracted below the trenches and the hole injected from the collector layer are attracted to the portions, wherein the electrons are accumulated, further increasing the accumulated carrier concentration.
When the ratio Wt/Wp is less than 1, electrons are not accumulated below the trenches similarly as in the conventional T-IGBT. The ratio Wt/Wp of more than 20 is not practical, since the number of the trenches in a unit area is so small that the channel resistance components increase.